Implement a NAND gate using only four CMOS transistors. Draw the CMOS NAND gate to aid in writing the Verilog code. The automatic testing does not ensure that only transistors were used. The submission will be manually reviewed to check if only transistors were used.Exercise 2 [2.0]LOCKEditor module nandgate(output logic y, input logic a, b; supply vdd; supply gnd; wire gateout;Test BenchSimulation OutputRun// Using only PMOS, NMOS, and wires, implement a NAND gateassign y = gateout;endmodule

NAND, NOR & XOR Logic Gates

Realizing Full Subtractor using NAND Gates only (Part 2) Video Lecture | Crash Course for GATE ECE (English) - Electronics and Communication Engineering (ECE)

Implement a full subtractor using a XOR gate, two AND gates, an... | Filo

Logic Gates using NAND and NOR universal gates