EDN

Advanced switch memory architectures improve network performance

The impact of memory architecture is a much researched, but little publicized element to the performance of today's network switches.Many academic papers have been written about the advantages of ...
TechRepublic

Cache-Only Memory Architecture

A Cache-Only Memory Architecture design (COMA) may be a sort of Cache-Coherent Non-Uniform Memory Access (CC- NUMA) design. not like in a very typical CC-NUMA design, in a COMA, each shared-memory ...
EDN

Memory models for embedded multicore SoCs, Part 1 – Memory architecture

Editor's Note: Multicore architectures find use across a diverse range of applications thanks to their performance and efficiency. By combining several general-purpose MCU cores — or MCU cores and ...
Semiconductor Engineering

Automation Of Shared Bus Memory Test With Tessent MemoryBIST

Shared bus interfaces and memory test These days, designs contain a huge number of memory arrays embedded in the core, and these memories often consume a substantial portion of the total chip area.
Semiconductor Engineering

Automate Memory Test Through A Shared Bus Interface

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point ...
CNET

Memory-shared supercomputer lands in Spain

Finis Terrae, Europe's largest memory-shared supercomputer, will tackle international research projects and be furnished by HP and Intel. In a software-driven world, it's easy to forget about the nuts ...