IEEE

Design and Simulation of a Carry Save Adder (CSA) using NAND Gate in CMOS 180nm Technology

Abstract: Using CMOS 180nm technology, this study explores the design and simulation of digital circuits which include basic logic gates to Carry Save Adder (CSA). With a focus on optimizing power ...
IEEE

Design and Evaluation of a Hybrid Adder Employing the Power Gating Method

Abstract: The multiplexers (mux) select the final sum and carry, rendering the CSLA an inefficient area adder. Two rows of ripple carry adders are present. While the suggested AFPL logic can reduce ...