EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. — Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
Electronic Design

Open Verification Methodology Relieves Inefficiencies

Since the IEEE’s adoption of SystemVerilog as IEEE Standard 1800-2005, and EDA vendors’ subsequent release of products supporting that standard, the semiconductor verification teams my company serves ...
EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. – Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
Semiconductor Engineering

Blog Review: July 21

Cadence’s Paul McLellan listens in as Partha Ranganathan of Google argues that a new era of Moore’s Law is emerging, defined both by the efficient design of hardware accelerators and improving the ...